1. Field of the Invention
The present invention relates to a general-purpose logic cell, a general-purpose logic cell array in which the general-purpose logic cells are formed in an array, and an ASIC using the general-purpose logic cell array.
2. Description of the Related Art
A cell array is conventionally known, from which a logic circuit is formed by forming a wiring line layer for connecting a plurality of cells on a lower layer in which the plurality of cells are arranged in an array. Thus, a semiconductor integrated circuit device with a desired function can be manufactured.
As such a cell array, for example, a cell array of a gate array type (hereinafter, to be referred merely to as “a gate array”) is known in which basic cells are arranged in an array. In the gate array, a lower layer is prepared in which the basic cells are arranged but wiring lines are not formed. All the connections are accomplished by forming a wiring line pattern in a wiring line layer which is formed in accordance with a logic circuit designed by a user. According to the gate array, the application of the basic cells is determined based on the logic circuit designed by the user. Therefore, transistors with a large size having high drive ability are adopted as transistors of the basic cell, in order to make the basic cells applicable to all the applications. As a result, a high gate density and low power consumption are hindered.
For this reason, a cell array is developed for a semiconductor device in which an exclusive use cell is optimized for a specific logic circuit, e.g., a flip-flop circuit. The cells are provided for a lower layer, and the exclusive use cells are primarily allocated to the flip-flop contained in the logic circuit designed by the user. For example, Japanese Laid Open Patent Application (JP-A-Heisei 11-265998) describes a semiconductor device and a manufacturing method suitable to form a semiconductor device desired electric circuit by a automatic arrangement wiring method. As shown in FIG. 1, the semiconductor device has a transistor forming area in which a specific function bank of transistors which are optimized for a flip-flop circuit, and a general-purpose function bank having a transistor arrangement in accordance with a conventional gate array method are alternately provided.
According to the semiconductor device disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-265998), it has advantages that the semiconductor device can be formed in a high gate density to have low power consumption, since the transistors of the exclusive use cell optimized for the flip-flop circuit are not necessary to have high drive ability unlike the transistors of the previous basic cell.
However, in the technique disclosed in the Japanese Laid Open Patent Application (JP-A-Heisei 11-265998), there is a case where a defect is found in the logical function of a logic circuit in the process after an arrangement process when the logic circuit designed by the user is formed in the lower layer, or a case a defect is found that a timing condition is not met because of shortage of a setup time or a hold time of the flip-flop. In such a case, if no elements necessary for repairing are in the neighborhood of at a defect portion, it is necessary to carry out the processes from the arrangement process again. As a result, the term of development of the semiconductor device becomes long and the development cost becomes high.
In conjunction with the above description, a gate array is described in Japanese Laid Open Patent Application (JP-A-Heisei 5-167048). In this conventional example, a plurality of NAND circuit cells or NOR circuit cells are formed with no wiring connection. By connecting the inputs or outputs of these circuits, a desired circuit is formed.